1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and more particularly to a method for fabricating a semiconductor device in which a plug is self-aligned and comes into contact with an impurity region composing a memory device within a cell area.
2. Description of Related Art
As the degree of integration of a semiconductor device increases, the size of a unit transistor decreases, and accordingly, the size of an impurity region serving as source and drain regions decreases. Consequently, the size of a contact hole for connecting the impurity region to a storage electrode of a capacitor or a bit line decreases. The contact hole decreases not in thickness but in size, so the ratio of length to breadth of the contact hole increases. Accordingly, it becomes difficult to form the contact hole for exposing the impurity region and connecting the impurity region to the storage electrode of the capacitor or the bit line. Furthermore, it is difficult to form the storage electrode of the capacitor or the bit line within the contact hole. These problems caused by the increase in the ratio of length to breadth of the contact hole appear more seriously in a memory device formed within the cell area of a smaller size than in a driver circuit device formed within a peripheral circuit area of a larger size.
To solve these problems, techniques are developed for forming at least two contact holes for formation of the storage electrode of the capacitor or the bit line in the memory device within the cell area, that is, for forming a plug in a lower contact hole exposing the impurity region and forming the storage electrode of the capacitor or the bit line to come into contact with the plug in an upper contact hole. The at least two contact holes including the lower and upper contact holes are reduced in their depth, as compared with the contact hole that is typically formed through a single process. According to the above techniques, the ratio of length to breadth of the contact hole is decreased, thereby allowing easy formation of the storage electrode of the capacitor and the bit line as well as the contact hole.
FIGS. 1A to 1E are diagrammatic illustrations showing a method for fabricating a semiconductor device according to a prior art.
Referring to FIG. 1A, a field oxide layer 13 is formed by STI (shallow trench isolation) on a p type semiconductor substrate 11 including a cell area C1 and a peripheral circuit area P1 to define active region and field region. The field oxide layer 13 is formed in such a manner that a pad oxide layer (not shown) and a masking film (not shown) are formed to expose a specified portion of the semiconductor substrate 11, subsequently, a trench 12 is formed at a predetermined angle at the exposed portion of the semiconductor substrate 11 by anisotropic etching such as RIE (reactive ion etching), the trench 12 is filled with silicon oxide, and then the masking film and the pad oxide layer are removed.
Referring to FIG. 1B, a gate insulating layer 15 is placed on the exposed portion of the semiconductor substrate 11 to form first and second gates 17 and 18 and capping layers 19 thereon. The first and second gates 17 and 18 and the capping layers 19 are formed in such a manner that, after forming the gate insulating layer 15 by thermal oxidizing the exposed portion of the semiconductor substrate 11, polysilicon and silicon nitride are deposited on the gate insulating layer 15 by CVD (chemical vapor deposition) and then patterned by photolithography including the anisotropic etching such as RIE. The first and second gates 17 and 18 may be formed in a double layers structure of polysilicon and silicide, and the capping layer 19 may be formed of silicon oxide.
An n type impurity is ion-implanted into the exposed portion of the semiconductor substrate 11 at a low dose using the capping layer 19 as a mask to form first and second impurity regions 21 and 23 in the cell area C1 and peripheral circuit area P1 respectively. The first impurity region 21 formed in the cell area C1 is used as source and drain regions composing the memory device together with the first gate 17. The second impurity region 23 formed in the peripheral circuit area P1 is used as a lightly doped drain (LDD) of the driver circuit device including the second gate 18.
Referring to FIG. 1C, silicon nitride is deposited over the entire surface of the resultant structure described above by the CVD to form an etching stop layer 25. An insulating material such as BPSG (boro phospho silicate glass) is deposited on the etching stop layer 25 to form a planerization layer 27. Because the BPSG composing the planarization layer 27 has a good fluidity, it not only fills a gap between the first and second gates 17 and 18 but also planarizes the surface of the resultant structure.
The planarization layer 27 in the peripheral circuit area P1 is patterned by the photolithography including the anisotropic etching such as RIE, thereby exposing the etching stop layer 25. At this time, the etching stop layer 25 is not removed because its etching selection ratio is different from that of the planarization layer 27. Accordingly, the etching stop layer 25 prevents the semiconductor substrate 11 and the filed oxide layer 13 from being etched during the patterning of the planarization layer 27.
Referring to FIG. 1D, a side wall spacer 29 is formed by the side of the second gate 18. The side wall spacer 29 is formed in such a manner that silicon oxide is deposited on the etching stop layer 25 and the planarization layer 27 by the CVD and then etched back by the RIE or the like. At this time, an exposed portion of the etching stop layer 25 in the peripheral circuit area P1 is etched, thereby exposing the semiconductor substrate 11 and the capping layer 19.
An n type impurity is ion-implanted into the exposed portion of the semiconductor substrate 11 at a high dose to be superposed on the second impurity region 23 by using the capping layer 19 and the side wall spacer 29 as the mask to form a third impurity region 31 which serves as source and drain regions of the driver circuit device including the second gate 18 and the second impurity region 23.
Referring to FIG. 1E, an interlevel insulating layer 33 is formed by depositing silicon oxide over the planarization layer 27 and the driver circuit device including the second gate 18 and the second and third impurity regions 23 and 31 in the peripheral circuit area P1 through the CVD. Because a step difference between the cell area C1 and the peripheral circuit area P1 is large due to the planarization layer 27, the interlevel insulating layer 33 is formed in thickness of 1 .mu.m to reduce the step difference between the cell area C1 and the peripheral circuit area P1.
A photoresist (not shown) is formed on the portion of interlevel insulating layer 33 corresponding to the peripheral circuit area P1 and then an exposed portion of the cell area C1 is etched back by the RIE to remove the step difference, thereby planarizing the entire surface. The remaining interlevel insulating layer 33 is removed by chemical-mechanical polishing (CMP). As a result, the interlevel insulating layer 33 in the cell area C1 is left only in thickness of about 1000.about.2000 .ANG..
Portions of the interlevel insulating layer 33, the planarization layer 27, and the etching stop layer 25 corresponding to the first impurity region 21 within the cell area C1 are sequentially patterned by the photolithography including the anisotropic etching such as RIE to form a contact hole 35 exposing the first impurity region 21.
Polysilicon is deposited on the interlevel insulating layer 33 by the CVD, thereby filling the contact hole 35 and coming into contact with the first impurity region 21. A plug 37 is formed in such a manner that the polysilicon is etched back by the RIE or the CMP, exposing the interlevel insulating layer 33 and leaving the polysilicon only in the contact hole 35.
In the conventional method for fabricating a semiconductor device as described above, since the planarization layer must be patterned to form the side wall spacer by the side of the second gate in the peripheral circuit area and the planarization layer of the peripheral circuit area must be formed to planarize the interlevel insulating layer that is formed on the patterned structure thinly, fabricating processes are complicated. Furthermore, the conventional method uses the CMP to form the thin interlevel insulating layer, which makes it difficult to control the thickness precisely, thereby limiting the thinness of the interlevel insulating layer. This increases the ratio of length to breadth of the contact hole, thereby making it difficult to form the plug.